MOCS (SHARP) - séminaire poster 2020

En mode distanciel

Monday, December 14, 2020

Le séminaire poster aura lieu en mode virtuel le 14 décembre 2020, à partir de 14h.

Le séminaire poster permet de réunir les collègues de toute l'équipe et d'échanger autour d'un poster, déjà présenté lors d'une manifestation scientifique ou créé pour l'occasion.

Pour proposer un poster, une seule règle : envoyez un email à Kevin Martin et Frank Singhoff pour le 7/12/2020.

Voyons les avantages du mode distanciel : pas de perte de temps dans les déplacements, logistique allégée (pas de poster à imprimer, pas de repas ou pause café à prévoir, pas de support à installer, ...)

Le programme préliminaire

- 14h : arrivée virtuelle
- 14h - 14h45 : échanges réels dans les salons virtuelles
- 14h45 - 15h15 : Pause virtuelle (chacun prépare sa boisson et ses petits gâteaux...)
- 15h15 - 16h00 : échanges réels dans les salons virtuelles
- 16h : Bilan en fin de séminaire.

ARCAD - Subutai: Distributed synchronization primitives for legacy and novel parallel applications

Rodrigo Cadore CATALDO - 14h

Monday, October 19, 2020

Parallel applications are essential for efficiently using the computational power of a MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. The existing solutions either restrict the application to a subset of synchronization primitives, require refactoring the source code of it, or both.
We introduce Subutai, a hardware/software architecture designed to distribute the synchronization mechanisms over the Network-on-Chip. Subutai is comprised of novel hardware specialized in accelerating synchronization operations, a small private memory for recording events, an operating system driver, and a user space custom library that supports legacy and novel parallel applications.

We target the POSIX Threads (PThreads) library as it is widely used as a synchronization library, and internally by other libraries such as OpenMP and Threading Building Blocks. We also provide extensions to Subutai intended to further accelerate parallel applications in two scenarios: (i) multiple applications running in a highly-contended scheduling scenario; (ii) remove the access serialization to condition variables in PThreads. Experimental results with four applications from the PARSEC benchmark running on a 64-core MPSoC show an average application speedup of 1.57× compared with the legacy software solutions. The same applications are further sped up to 5% using our proposed Critical Section-aware scheduling policy compared to a baseline Round-Robin scheduler without any changes in the application source code.


Thesis online

ARCAD - Réseaux de permutations pour les codes correcteurs : modèles et architectures

Cyrille Chavet

Tuesday, February 25, 2020

CR114 pour les lorientais.

Avec la fin du projet FlexDEC-5G, projet orienté autour d'architectures flexibles pour la 5G notamment, je souhaite profiter de cette occasion pour retracer les travaux que nous avons menés depuis mon arrivé au sein du Lab-STICC. Ce séminaire proposera une présentation simplifiée de la problématique étudiée et de l'état de l'art, avant d'explorer les différents travaux menés ces dernières années. Ce séminaire se conclura sur l'impact des dernières évolutions des codes correcteurs (3GPP-LTE et 5G) sur la problématique.

Adopting Memristors for In-Memory Computation

Mostafa Rizk

Friday, December 6, 2019

The aggressive growth in the size of processed data in addition to the increasing numbers of processing cores have placed a high demand on the currently used memory systems. Emerging memristive technologies such as the resistive RAM (RRAM) or magneto-resistive RAM (MRAM) have been considered as promising candidates for the next generation of memories. Memristive memory systems have several desirable attributes. They are classified as non-volatile with near-zero standby power consumption. They have ultra high density. Recent studies have illustrated the ability to perform local computations inside memristive memories (crossbars). This type of computations is referred as in-memory computing. The major interests with such computations inside memory is that they could be performed without the need to move data from memory to processing cores and back. Thus, accelerating the application performance and minimizing the bottleneck access of memory.
Several works have been carried out revealing the ability to execute logic operations inside memristive memory. In this seminar the use of memristors will be illustrated in performing in-memory computations. A new proposed method for computing inside memristive namely the Memristor overwrite logic (MOL) will be thoroughly introduced.

Download : [pdf] Slides of the seminar (4.13 Mo)

ARCAD - Implantation d'algorithmes à l'aide de circuits analogiques


Friday, December 13, 2019

Début à 10h30, visio à partir de 10h15.

Safe and Secure Internet of Flying Things, Research and Challenges

Kalinka Branco

Tuesday, July 2, 2019

Autonomous vehicles (aerial, ground, underwater, etc) are going to invest human environment and due to their characteristics, they are natural candidates to integrate the Internet of Things (IoT). By including autonomous vehicles into IoT, it will be possible to compose the Internet of Mobile Things (IoMoT), which introduces new opportunities and challenges. IoMoT raises challenges related to scalability, group control, synchronization, power consumption, limited embedded resources and limited action time so an important turnover. Considering the required multidisciplinary in the development of embedded systems and that all these dimensions introduce manifold security and safety issues, this talk will focus on security considering the global future IoMoT context outlining some research opportunities and challenges brought by the insertion of Unmanned Aerial Vehicles (UAVs) into IoMoT and an overview of efforts in research and innovation in Embedded Systems in Critical Embedded System Laboratory at USP.

ARCAD - Introduction to Post Quantum Cryptography

Timo Zijlstra

Thursday, July 4, 2019

Cryptographic key exchange protocols make use of the computational difficulty of certain mathematical problems. The protocols are designed in such a way that finding a fast algorithm to break the cryptosystems would be equivalent to a mathematical breakthrough. RSA for instance, relies on the assumption that there is no polynomial time algorithm to solve the large integer factorization problem. Shor's quantum algorithm shows that this assumption is false. RSA and other cryptographic standards such as ECC, can effectively be broken using a quantum computer. It is therefore important to develop new cryptographic algorithms that are safe in a quantum world. In 2016, the NIST launched a project to select and standardize post quantum cryptographic algorithms. In this talk we will discuss the threat that quantum computing poses to security and introduce some of the proposed solutions.

MOCS - séminaire poster 2019


Tuesday, April 30, 2019

Le séminaire poster permet de réunir les collègues de toute l'équipe et d'échanger autour d'un poster, déjà présenté lors d'une manifestation scientifique ou créé pour l'occasion.

Chaque poster fait l'objet d'un "teaser", présenté devant l'assemblé.

Les teasers pour cette session 2019 sont disponibles dans le fichier ci-dessous.
Un template pour vous aider à élaborer une seule planche qui résume rapidement le poster est proposé.
Utiliser le template n'est pas obligatoire. Une seule règle : une seule page en pdf !
à renvoyer à Kevin Martin pour le 23/04/2019 à 18h.

Il n'y a pas de service d'impression sur place.
! Les exposants doivent venir avec leur poster imprimé !

Rendez vous à l'amphi Sciences 2 à 12h (UFR sciences, rue Saint Maudé à Lorient).
Rendez-vous pour tout le monde à 13h30 à l'amphi Sciences 2.
Présentation de tous les posters en mode "teaser" (90 secondes) à partir de 13h30.
Tour des posters vers 14h.
Bilan et fin du séminaire prévus vers 16h/16h30.

Download : [pdf] 1allteasers-seminarpostermocs2019.pdf (4.43 Mo)

ARCAD - Energy efficient application mapping onto CGRAs


Monday, April 29, 2019

Presented by Satyajit Das.

Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as a low power computing alternative providing a high grade of acceleration. However, the area and energy efficiency of these devices are bottlenecked by the configuration/context memory when they are made autonomous and loosely coupled with CPUs. The size of these context memories is of prime importance due to their high area and impact on power consumption. For instance, a 64-word context memory typically represents 40% of a processing element area. In this context, since traditional mapping approaches do not take the size of the context memory into account, CGRAs often become oversized which strongly degrade their performance and interest. In this work, we proposed a context memory aware mapping for CGRAs to achieve better area and energy efficiency. In my talk, I will describe the proposed mapping approach which tries to find at least one mapping solution for a given set of constraints defined by the context memories of the PEs. Another important aspect of application mapping is addressed in this work, which is to support floating point applications onto CGRAs. With the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this work, we proposed a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration. In my talk, I will also speak about the proposed architecture and compilation flow supporting floating point operations onto CGRAs.

ACID/P4S - Contrôle sûr de chaines d'obfuscation logicielle


Thursday, April 18, 2019

Nicolas Szlifierski

L'obfuscation est une technique de protection logicielle qui consiste à modifier a forme exécutable d'un programme de façon à ce qu’il devienne difficile de comprendre son fonctionnement ou d’en extraire des informations. Au-delà de la problématique liée à la propriété intellectuelle, son utilisation est indispensable pour protéger ou cacher certaines informations ou algorithmes sensibles contenus dans un logiciel comme une clé cryptographique ou un système de DRM. De nombreux mécanismes d’obfuscation ont été proposés et consistent, en général, en des transformations de code qui doivent être réalisées pendant ou après la compilation. Contrairement aux transformations d’optimisation qui peuvent en général être appliquées sur tout le programme, les transformations d’obfuscation doivent être appliquées plus finement afin d’obtenir un compromis entre la protection et les performances, ce qui rend les gestionnaires de passes des compilateurs traditionnels peu adaptés à l'obfuscation. Nous proposons un langage dédié à la définition fine et l'exécution sûre de chaines de compilation contenant des transformations d'obfuscation.

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